The present disclosure relates to semiconductor devices and methods for manufacturing the semiconductor devices, and specifically relates to semiconductor devices including a chip-on-chip structure in which a plurality of semiconductor chips are stacked with each other, and methods for manufacturing the semiconductor devices.
In systems such as digital televisions and recorders, data amount to be processed has been significantly increasing with increased functionality. The capacity of semiconductor memories mounted on the systems is accordingly increasing. Further, semiconductor memories with high data transfer rate have been demanded. Semiconductor devices in which a logic circuit including a memory controller and a memory are integrally mounted have been developed so that a lot of semiconductor memories can be mounted on the system.
Techniques of integrally forming a logic circuit and a memory include a system-on-chip (SoC) technique in which a logic circuit chip and a memory chip are integrated on one chip, and a system-in-package (SiP) technique in which a logic circuit chip and a memory chip are stacked with each other and accommodated in one package. According to the SiP technique, the chips can be produced at lower costs, have higher functionality, consume less power, and can be reduced in size and weight, as demanded, and can be flexibly applied to various specifications. Therefore, systems utilizing the SiP structure with relatively low manufacturing cost are now increasing.
The SiP structure is classified into four types according to differences in the structure, i.e., a chip-on-chip (CoC) type, a stacked chip type, a package-on-package type, and a substrate connection type. Among these types, the CoC type has a structure in which a chip is stacked on a base chip, and this structure enables high speed processing due to a short interconnection length between circuits provided at the respective chips.
In conventional CoC semiconductor devices, the technique for connecting chips whose circuit sides face each other includes connection through bumps (see, e.g., Japanese Unexamined Patent Publication No. 2004-146728).